1. Field of the Invention
The present invention relates to synchronous electronic circuits, and, more particularly, to clock signal generation and control.
2. Description of the Related Art
In synchronous digital information processing equipment it is well known to use a clock source for developing control signals to time and synchronize circuit operations. It is common to utilize an oscillator circuit to produce a basic source frequency signal, which in turn is utilized to drive shaping circuitry for developing the desired rise and fall time and desired signal levels. The clock rate requirements for timing digital information processing systems are proportional to the switching speeds of the circuitry employed. As clock rates increase, tolerances are necessarily diminished, and clock skew becomes an ever-increasing problem. Furthermore, the duty cycle in synchronous digital systems is extremely critical when logic is synchronous to both the rising and falling edges of the clock (as is common in high performance processors for instance). A duty cycle error of just 5% for instance (from 50% to 45%) can actually cause a system clock to run at a maximum speed that is 10% lower, causing a significant impact on system performance.
Many circuits require a specific duty cycle for clocking signals to provide optimal performance. For example, multi-phase clocking systems often require a symmetrical wave shape that is characteristically desired to operate at a 50% duty cycle. Some applications require a duty cycle other than 50%. One use of non-50% duty cycles is in digital clocking where pulse-mode latching is used rather than edge-latching in order to reduce the setup-hold overhead associated with the latches. Control of the clock duty cycle is very critical in these higher performance systems. The precision of the duty cycle operation is especially critical in systems that utilize edge or transition triggering for generation of multi-phase clock signals, and is even more critical when both leading and trailing edges are utilized to generate the phase clocking signals. If a trailing edge of a clock signal varies from the leading edge of the clock signal, logic that triggers on the leading edge may have a tighter timing margin that logic that triggers on the trailing edge, or vice versa. Thus, there is a need for a duty cycle control technique that can target either or both of 50% and non-50% duty cycles.
Actual duty cycles typically do not have precisely the desired value. Even if a clock signal has the required duty cycle at some point in the system (e.g., at the output of an on-chip voltage controlled oscillator), the duty cycle will deviate from the required percentage as the clock signal is buffered and distributed throughout the chip. The buffer stages will give different duty cycle errors depending on process, temperature, and voltage conditions. In many cases, the desired duty cycle is not even available out of the voltage controlled oscillator (VCO) on chip or at the clock signal input of the chip. Thus, there is a need to control the duty cycle actively.
The basic function of a duty cycle adjustment circuit is to measure the error of the duty cycle and provide a correction signal to reduce that error. One approach to adjusting a duty cycle is disclosed in T. Lee, et al., "A2.5V Delay-Locked Loop for an 18 Mb 500 MB/s DRAM,"IEEE Int'l Solid-State Circuits Conf., Digest of Technical Papers, pp. 300-1, 1994. In Lee, a charge pump switches equal currents and creates the error measurements. However, this reference assumes that a complementary clock signal is being 50% duty cycle adjusted. Complementary clocks require additional generation and matching circuits if only a simple single-ended clock is needed. Also this method does not allow for any duty cycle other than 50% to be targeted. A similar approach is disclosed in S. Siridopoulos, M. Horowitz, "A700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers,"IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 681-690, May 1997. The Siridopoulos duty cycle correction technique is similar in principle to the Tom Lee reference and inherits its problems.
Another approach is disclosed in A. Waizman, "A Delay Line Loop for Frequency Synthesis of De-Skewed Clock,"IEEE Int'l Solid-State Circuits Conf., Digest of Technical Papers, pp. 298-9, 1994. In Waizman, a single delay line delays the rising edge of an input clock twice and recycles the delayed edge one time rather than delaying the falling edge of the input clock. This method only targets a 50% duty cycle and is therefore limited in use if other duty cycles are desired. Also, the high to low delay through a delay line does NOT in general match the low to high delay through a delay line. Thus, there is also a static duty cycle error that is actually created by this technique.
Thus, there is a need to actively control clock signal duty cycles. There is also a need for such an active duty cycle control technique that can target non-50% duty cycles. It is desirable that such a control technique be simple, minimize jitter added by the control circuitry, and reduce or eliminate any static duty cycle errors that can be created by the adjustment circuit.